The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions multiplications without carry propagation between residue digits. The parallelism fault-tolerance features of RNS can be leveraged reversible computing. This paper proposed full circuits, including forward converters, modular adders multipliers, reverse converters used a class moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1 multipliers were designed using gates. Besides, 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. RNS-based approach has applied consecutive improvement above 15% in quantum cost after twelfth iteration, 27% depth ninth iteration. findings show that use convolution results significant comparison conventional methods based on weighted binary multipliers.